The present invention relates to a logic circuit which operates on different voltages, for example, voltages of a normal logic level and a high logic level.
A E.sup.2 PROM (Electrically Erasable and Programmable ROM) operates on a high voltage (20 V or more) when new information is written in the E.sup.2 PROM. However, it is required that the E.sup.2 PROM uses only 5 V power supply and does not need a separate high voltage supply for programming. For this reason, the E.sup.2 PROM usually has a circuit for boosting a voltage from 5 V to 20 V. The boosting circuit in the E.sup.2 PROM generally has a high impedance and is capable of producing only a limited current. Therefore, a logic circuit of the type operating on both a normal voltage and a high voltage, such as a E.sup.2 PROM, should require only a low power dissipation.
FIG. 1 shows a conventional logic circuit of the above-mentioned type. The logic circuit has an input terminal 1, an output terminal 2, a terminal 3 to which the normal voltage (5 V) is applied, and a terminal 4 to which the normal voltage (5 V) or the high voltage (20 V) is selectively applied. A voltage V.sub.2 on the output terminal 2 ranges from 0 V to 5 V when the normal voltage (5 V) is applied to the terminal 4. The voltage V.sub.2 ranges from 0 V to 20 V when the high voltage is applied to the terminal 4.
In the logic circuit, while the voltage V.sub.PP applied to the terminal 4 is raised from 5 V to 20 V, a large through current flows in the logic circuit. This result in a large power dissipation. If the ability of a boosting circuit 6 is not enough to supply the large through current, the boosting circuit 6 cannot raise the voltage V.sub.2 to the high voltage.
Further consideration is given to the above-mentioned problem. First, it is assumed that an NMOS transistor 7 is conductive and a voltage V.sub.5 of a line 5 is at a low level. When the voltage V.sub.PP of the terminal 4 is increased, the voltage V.sub.2 of the output terminal 2 is increased following a rise in the voltage V.sub.PP. However, the increase in the voltage V.sub.2 of the output terminal 2 lags behind the increase in the voltage V.sub.PP. Thus during the increment of the voltages, the relationship between the voltages V.sub.2 and V.sub.PP is as follows: EQU .vertline.V.sub.2 -V.sub.PP .vertline.&gt;.vertline.V.sub.thp .vertline.,
where V.sub.thp is a threshold voltage of a PMOS transistor 9. Thus PMOS transistor 9 is on. As the PMOS transistor 9 and the NMOS transistor 7 are on at the same time, a through current is generated which flows from the terminal 4 to a power source V.sub.SS via the PMOS transistor 9, the line 5 and the NMOS transistor 7.
Secondly, it is assumed that the voltage V.sub.5 is at a high level. Then, an NMOS transistor 10 is on, and a PMOS transistor is on because the voltage 2 is at a low level. When the voltage V.sub.PP is increased, the voltage V.sub.5 is increased following a rise in the voltage V.sub.PP. However, the increase in the voltage V.sub.5 of the line 5 lags behind the increase in the voltage V.sub.PP. Thus, during the increment of the voltages, the relationship between the voltages V.sub.5 and V.sub.PP is as follows: EQU .vertline.V.sub.PP -V.sub.5 .vertline.&gt;.vertline.V.sub.thp .vertline.
where V.sub.thp is a threshold voltage of a PMOS transistor 8. Thus the PMOS transistor 8 is on. As the PMOS transistor 8 and the NMOS transistor 10 are on at the same time, a through current is generated.
As described above, a large through current is generated in the conventional logic circuit during a rise in the voltage V.sub.PP. FIG. 2 shows a E.sup.2 PROM which includes drivers 12 using the logic circuits. N drivers 12 are connected to M cells 13, respectively. A boosting circuit 11 is common to the N drivers 12. When the voltage V.sub.PP is raised from 5 V to 20 V, the boosting circuit 11 must drive the N drivers 12 to supply all N through currents of the drivers 12. If a storage capacity of the E.sup.2 PROM is 64 kilo bits, the number N is 256. The sum of 256 through currents is so large that the boosting circuit 11 cannot supply them. Thus the boosting circuit 11 cannot raise an output voltage of the drivers 12 to the high voltage. Even if the boosting circuit 11 can raise the output voltage of the drivers 12, its waveform is greatly distorted. And also the large through currents result in a large power dissipation.